Essays about: "Verilog"
Showing result 6 - 10 of 48 essays containing the word Verilog.
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6. A Digital Design Flow - From Concept to RTL Description, Using Mathworks and Cadence's Tools
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : This report presents our digital design flow for creating high speed very large scale integration circuits using a fifth generation disruptive beamforming control and data processing circuit as example. The flow consists of different stages. READ MORE
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7. Network Implementation with TCP Protocol : A server on FPGA handling multiple connections
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : The growing number of players in Massively Multiplayer Online games puts a heavy load on the network infrastructure and the general-purpose CPU of the game servers. A game server’s network stack processing needs equal treatment to the game-related processing ability. READ MORE
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8. Design space exploration using HLS in relation to code structuring
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : High Level Synthesis (HLS) is a methodology to translate a model developed in a high abstraction layer, e.g. C/C++/SystemC, that describes the algorithm into a Register-Transfer level (RTL) description like Verilog or VHDL. READ MORE
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9. Validation of efficiency of formal verification methodology for verification closure
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : Application Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) verification is quite a time consuming phase in design flow cycle and it can be done using methodologies such as Universal Verification Methodology (UVM) and formal verification.The UVM methodology is simulation based verification where in the verifier will have to trigger the Design Under Test (DUT) manually by writing sequences which target different features of the DUT and the verification environment can also have verification directives such as assertions to spot design bugs. READ MORE
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10. Design of a 12-bit 200-MSps SAR Analog-to-Digital converter
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : The Successive Approximation (SAR) Analog-to-Digital converter is one of the most energy-efficient A/D converter. In this thesis, the development of a SAR ADC in a 28-nm CMOS technology based on charge redistribution is presented. READ MORE
