Essays about: "adc verilog"
Found 5 essays containing the words adc verilog.
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1. Design of a 12-bit 200-MSps SAR Analog-to-Digital converter
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : The Successive Approximation (SAR) Analog-to-Digital converter is one of the most energy-efficient A/D converter. In this thesis, the development of a SAR ADC in a 28-nm CMOS technology based on charge redistribution is presented. READ MORE
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2. High-Speed Hybrid Current mode Sigma-Delta Modulator
University essay from Elektroniksystem; Tekniska högskolanAbstract : The majority of signals, that need to be processed, are analog, which are continuous and can take an infinite number of values at any time instant. Precision of the analog signals are limited due to influence of distortion which leads to the use of digital signals for better performance and cost. READ MORE
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3. Ultra low power Analog-to-Digital Converter for Biomedical Devices
University essay from KTH/Skolan för informations- och kommunikationsteknik (ICT)Abstract : The biomedical devices often operate only with a battery, e.g., blood glucose monitor, pacemaker. Therefore, it is desirable to fully utilize the energy without sacrificing the performance of the system. READ MORE
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4. Study of Time-Interleaved SAR ADC andImplementation of Comparator for High DefinitionVideo ADC in 65nm CMOS Process
University essay from ElektroniksystemAbstract : The Analog to Digital Converter (ADC) is an inevitable part of video AnalogFront Ends (AFE) found in the electronic displays today. The need to integratemore functionality on a single chip (there by shrinking area), poses great designchallenges in terms of achieving low power and desired accuracy. READ MORE
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5. Low-power 8-bit Pipelined ADC with current mode Multiplying Digital-to-Analog Converter (MDAC)
University essay from Institutionen för systemteknikAbstract : In order to convert the analog information in the digital domain, pipelined analog-to-digital converter (ADC) offers an optimum balance of resolution, speed, power consumption, size and design effort. In this thesis work we design and optimize a 8-bit pipelined ADC for low-power. The ADC has stage resolution of 1. READ MORE
