Essays about: "cmos adder design"
Found 5 essays containing the words cmos adder design.
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1. Complexity Reduction in the CORDIC Algorithm by using MUXes
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : Nowadays, the CORDIC algorithm plays an important role to deal with the non-linear functions in hardware. In this thesis, a novel methodology is described to reduce the complexity in an unrolled CORDIC architecture, which gives higher speed, lesser area, and lower power consumption. That is, MUXes are used to replace adder stages. READ MORE
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2. Design and implementation of an approximate full adder and its use in FIR filters
University essay from Elektroniksystem; Tekniska högskolanAbstract : Implementation of the polyphase decomposed FIR filter structure involves two steps; the generation of the partial products and the efficient reduction of the generated partial products. The partial products are generated by a constant multiplication of the filter coefficients with the input data and the reduction of the partial products is done by building a pipelined adder tree using FAs and HAs. READ MORE
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3. Design and Simulation of Miscellaneous Blocks of an All-Digital PLL for the 60 GHz Band
University essay from Elektroniksystem; Tekniska högskolanAbstract : A phase-locked loop commonly known as PLL is widely used in communication systems. A PLL is used in radio, telecommunications, modulation and demodulation. It can be used for clock generation, clock recovery from data signals, clock distribution and as a frequency synthesizer. Most electronic circuits encounter the problem of the clock skew. READ MORE
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4. An Energy-efficient 32-bit multiplier architecture in 90nm CMOS
University essay from Institutionen för systemteknikAbstract : A fast and energy-efficient multiplier is always needed in electronics industry especially DSP, image processing and arithmetic units in microprocessors. Multiplier is such an important element which contributes substantially to the total power consumption of the system. READ MORE
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5. Performance Analysis and Implementation of Full Adder Cells Using 0.18 um CMOS Technology
University essay from Institutionen för systemteknikAbstract : 0.18 um CMOS technology is increasingly used in design and implementation of full adder cells. Hence, there is a need for better understanding of the effects of different cell designs on cell performance, including power dissipation and time delays. READ MORE
