Essays about: "instruction-level"

Showing result 1 - 5 of 14 essays containing the word instruction-level.

  1. 1. Machine Learning-Based Instruction Scheduling for a DSP Architecture Compiler : Instruction Scheduling using Deep Reinforcement Learning and Graph Convolutional Networks

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Lucas Alava Peña; [2023]
    Keywords : Instruction Scheduling; Deep reinforcement Learning; Compilers; Graph Convolutional Networks; Schemaläggning av instruktioner; Deep Reinforcement Learning; kompilatorer; grafkonvolutionella nätverk;

    Abstract : Instruction Scheduling is a back-end compiler optimisation technique that can provide significant performance gains. It refers to ordering instructions in a particular order to reduce latency for processors with instruction-level parallelism. READ MORE

  3. 2. Improving the ecological validity of cognitive functions assessment through Virtual Environments : Results of a usability evaluation with healthy adults

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Simone Tafaro; [2023]
    Keywords : Virtual Reality; Cognitive Impairment; Ecological Validity; Virtual Environments; Virtuell verklighet; kognitiv funktionsnedsättning; ekologisk validitet; virtuella miljöer;

    Abstract : The early detection of mild cognitive impairment has the potential to significantly impact the lives of individuals who may be unaware of their cognitive decline. Such a condition can greatly affect their quality of life and ability to perform daily activities. READ MORE

  4. 3. Improving performance of BWA alignment of short sequences with coroutines

    University essay from Uppsala universitet/Institutionen för informationsteknologi

    Author : David Jonsson; [2021]
    Keywords : ;

    Abstract : For the Burrows-Wheeler Aligner (BWA), previous experimentation has shown that alignment of short sequences (reads) can benefit fromincreased instruction level parallelism (ILP) using hyperthreading.This thesis investigates and demonstrates that one can increase the performance of short read alignemnt with BWA without hyperthreading enabled, by employing coroutines in order to increase ILP. READ MORE

  5. 4. Implementing the Load Slice Core on a RISC-V based microarchitecture

    University essay from Uppsala universitet/Datorarkitektur och datorkommunikation

    Author : Axel Dalbom; Tim Svensson; [2020]
    Keywords : riscv; risc-v; ariane; evaluation; load slice core; lsc;

    Abstract : As cores have become better at exposing Instruction-Level Parallelism (ILP), they have become bigger, more complex, and consumes more power. These cores are approaching the Power- and Memory-wall quickly. A new microarchitecture proposed by Carlson et. al claims to solve these problems. READ MORE

  6. 5. Rapid Estimation of Energy Consumption for Embedded Software

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Benjamin Olayinka; [2019]
    Keywords : ;

    Abstract : Energy consumption is an important parameter very early in the design phase for embedded systems, especially battery powered systems. To obtain a cycle-accurate estimation of a program’s energy consumption, the program must be compiled and simulated on the target architecture, but this requires a hardware specification and complete code which may not be available early in the design phase. READ MORE