Essays about: "network-on-chip"
Showing result 11 - 15 of 33 essays containing the word network-on-chip.
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11. Analysing Real-Time Traffic in Wormhole-Switched On-ChipNetworks
University essay from Mälardalens högskola/Inbyggda systemAbstract : With the increasing demand of computation capabilities, many-core processors are gain-ing more and more attention. As a communication subsystem many-core processors, Network-on-Chip (NoC) draws a lot of attention in the related research fields. A NoC is used to deliver messages among different cores. READ MORE
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12. Erlang on Adapteva's Parallella
University essay from Uppsala universitet/Institutionen för informationsteknologiAbstract : By connecting many simple general-purpose RISC CPUs with a Network-on-Chip memory system, the Epiphany co-processor architecture provides promising power-efficiency. This thesis presents ParallErlang, a modified Erlang Runtime System, capable of running some actors on the Epiphany co-processor. READ MORE
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13. Short Message Network-On-Chip Interconnect for ASIC
University essay from KTH/Skolan för informations- och kommunikationsteknik (ICT)Abstract : The rise of large scale integration has resulted in large number of processing elements/cores on a single ASIC. Thus an efficient interconnect scheme between the different processing elements and interfaces is required. Bus based interconnect poses problems such as non-scalability. READ MORE
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14. Fuzzy Flow Regulation for Network-on-Chip based Chip Multiprocessors Systems
University essay from KTH/Skolan för informations- och kommunikationsteknik (ICT)Abstract : As large uniprocessors are no longer scaling in performance, chip multiprocessors (CMP) become the mainstream to build high-performance computers. CMP chips integrate various components such as processing cores, L1 caches and L2 caches (some also contain L3 caches, for example, in the IBM Power7 multicore processor) together, and multiple CMP chips with external memory banks make up a CMP system. READ MORE
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15. Fault-Tolerant Nostrum NoC on FPGA for theForSyDe/NoC System Generator Tool Suite
University essay from KTH/Elektronik och Inbyggda SystemAbstract : Moore’s law is the observation that over the years, the transistor density will increase,allowing billions of transistors to be integrated on a single chip. Over the lasttwo decades, Moore’s law has enabled the implementation of complex systems on asingle chip(SoCs). READ MORE
