Essays about: "pipeline vhdl"
Showing result 1 - 5 of 6 essays containing the words pipeline vhdl.
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1. Customized Processor Design for 5G Data Link Layer Processing
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : This thesis aims to explore the workflow related to designing an application specific instruction-set processor (ASIP). An ASIP is a processor similar to a hardware accelerator (HAC) in terms of performance and efficiency, but containing elements of general purpose processors (GPPs) when it comes to programmability and flexibility. READ MORE
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2. FPGA acceleration of superpixel segmentation
University essay from Mälardalens högskola/Inbyggda systemAbstract : Superpixel segmentation is a preprocessing step for computer vision applications, where an image is split into segments referred to as superpixels. Then running the main algorithm on these superpixels reduces the number of data points processed in comparison to running the algorithm on pixels directly, while still keeping much of the same information. READ MORE
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3. Hardware bidirectional real time motion estimator on a Xilinx Virtex II Pro FPGA
University essay from Institutionen för systemteknikAbstract : This thesis describes the implementation of a real-time, full search, 16x16 bidirectional motion estimation at 24 frames per second with the record performance of 155 Gop/s (1538 ops/pixel) at a high clock rate of 125 MHz. The core of bidirectional motion estimation uses close to 100% FPGA resources with 7 Gbit/s bandwidth to external memory. READ MORE
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4. Power Estimation of High Speed Bit-Parallel Adders
University essay from Institutionen för systemteknikAbstract : Fast addition is essential in many DSP algorithms. Various structures have been introduced to speed up the time critical carry propagation. For high throughput applications, however, it may be necessary to introduce pipelining. READ MORE
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5. A Synthesizable VHDL Behavioral Model of A DSP On Chip Emulation Unit
University essay from Institutionen för systemteknikAbstract : This thesis describes the VHDL behavioral model design of a DSP On Chip Emulation Unit. The prototype of this design is the OnCE port of the Motorola DSP56002. READ MORE