Essays about: "thesis using verilog"

Showing result 1 - 5 of 22 essays containing the words thesis using verilog.

  1. 1. Novel Method of ASIC interface IP development using HLS

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Anestis Athanasiadis; Chandranshu Mishra; [2023]
    Keywords : High Level Synthesis; HLS; Untimed C ; Control logic; I3C; clock-accurate design; IP development; Technology and Engineering;

    Abstract : High-Level Synthesis(HLS) is a design methodology that enables designers to implement hardware from high-level coding languages, such as C, C++, or System C. It provides designers with the ability to convey their design at a higher level of abstraction, which allows more emphasis on an algorithm and functional aspects of design instead on low-level hardware details. READ MORE

  3. 2. Exploring Ethernet Switching Architectures for Area-Efficient Low-End Switches

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Jon Swedberg; Felix Ghosh; [2023]
    Keywords : Ethernet Switch; Architecture; Silicon Area; Area Optimization; ASIC; FPGA; Technology and Engineering;

    Abstract : The aim of this thesis project has been to develop an architecture for L2 ethernet switches that would be optimized for silicon area, targeting smaller low-end switches. A selection was made of three different switching architectures, which were compared and analyzed to explore the benefits and drawbacks of different approaches. READ MORE

  4. 3. High Level Synthesis for ASIC and FPGA

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Malin Heyden; [2023]
    Keywords : HLS; high level synthesis; asic; fpga; catapult; filter; sfir; Technology and Engineering;

    Abstract : This thesis aims to evaluate the performance of Siemens’ High Level Synthesis (HLS) tool Catapult. HLS can be considered the next step up in abstraction level from writing traditional Register Transfer Level (RTL) code which is time consuming and error prone. READ MORE

  5. 4. D-band Power Amplifiers in Vertical InGaAs Nanowire MOSFET Technology for 100 Gbps Wireless Communication

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Patrik Blomberg; Ludvig Pile; [2022]
    Keywords : D-band; Power Amplifier; Pseudo-differential common source; Stacked; Vertical InGaAs nanowire; MOSFET; Technology and Engineering;

    Abstract : Two different topologies of power amplifiers (PAs) are designed in the frequency range 130-174.8 GHz for use in backhaul transmitters. These are the pseudo-differential common source (PDCS) and the single-ended stacked amplifier topologies. READ MORE

  6. 5. A Digital Design Flow - From Concept to RTL Description, Using Mathworks and Cadence's Tools

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Tor Hammarbäck; Jorge Deza Concori; [2022]
    Keywords : Technology and Engineering;

    Abstract : This report presents our digital design flow for creating high speed very large scale integration circuits using a fifth generation disruptive beamforming control and data processing circuit as example. The flow consists of different stages. READ MORE