2.4G ~ 10.4G Hz CMOS programmable Frequency Divider

Abstract: This master thesis is as a final project in the Division of Computer Engineering at the Department of Electrical Engineering, Linköpings University, Sweden. The purpose of the project is to design a wide frequency range programmable frequency divider used in a PLL circuit for ultra wide band system. 0.18 um tsmc CMOS technology is used in this project. A brief introduction of PLL circuits and UWB specifications are given in the report and the circuit design issue is presented. Post-layout simulation results are shown in the later part of the report. The focus of this project is to make the frequency divider work well in wide range and high speed. Therefore, how to shorten feedback circuits’ latency and how to reduce complexity of the circuits are the main problems. Logic gate merged technique is used to reduce transistor number and carefully drawing layout makes the circuit work well in post-layout simulation.