A Linear, Wide-band, Low-Power Receiver for Narrowband- Internet of Things (NB-IoT)

Abstract: Advancement of technology with the aid of new application, wireless communication has grown rapidly in the past two decades. Recently, in the wireless communication industry, Narrowband- Internet of Things (NB-IoT) is being discussed by everyone, as the most important emerging technology of the day. Being a wireless technology, owing to the exodus of devices to be connected, with due consideration to the data transfer requirements, and spectrum allowances, the 3rd Generation Partnership Project (3GPP) have standardized the technology with a list of specifications. In this thesis, a comprehensive study is conducted to find the most promising receiver front end architectures for an NB-IoT User Equipment (UE) which is highly integrable, has the least DC power consumption at its best performance and has the least price per unit. For NB-IoT, the 3GPP standard mandates the requirement of a receiver front end to be capable of tuning to signals within the frequency range 450MHz to 2200MHz, thus necessitating it to wide-band reception with better selectivity. By emphasizing upon the reduction of price per device demands, comparing the characteristic trade-offs of the various architectures, analysis of the typical receiver’s non-ideal factors and considering the specifications and requirements, an inductor-less, external Surface Acoustic Wave (SAW) filter-less Direct Conversion Receiver (DCR) has been chosen as the potential candidate. The study reveals that the Frequency Translational Noise Canceling (FTNC) receiver front end and gain switching receiver front end stand as the most promising receiver topologies. The former, with its two modes of operation, saves DC power, displays a decent linearity performance and a relaxed trade-off between noise figure and linearity; while the latter has the advantage of variable gain control at RF which supports lower DC power consumption in the presence of large wanted signal without compromising largely on noise figure. The simulated DC power consumption for each of the architectures have a maximum of 40mW at their best performance with DSB noise figure ≈ 2dB, impedance matching <-15dB, <-70dBm spurious emission from LO divider circuits, and 3rd order harmonic rejection >40dB. The study is conducted in 40nm CMOS technology.