FPGA-BASED HYBRID COMPUTING FOR ESS LINAC SIMULATOR.

Abstract: The thesis explores efficient implementation strategies for the European Spallation Source (ESS) linear accelerator simulator. The target simulator needs to run at real time, requires high computation accuracy, and should be scalable for high density beam scenarios. The high data processing, communication, and storage requirements due to a large data set, along with a strict accuracy requirement, poses a critical implementation challenge for traditional computing platforms. To tackle these issues, this thesis uses a scalable platform with hybrid computing capabilities and the OpenCL framework for an unified programming model. The hybrid computing platform allows for mapping tasks to the most suitable hardware and explores heterogeneous memory hierarchy to fast data shuffling. The OpenCL framework allows functional portability and scalability across different target devices such as CPU, GPU and OpenCL accelerator devices like with FPGA and DSP arrays. The computational intensive tasks of the simulator can be conveniently mapped to the accelerators, where computational parallelism is explored. The targeted simulator is implemented in a Xilinx hybrid computing platform, consisting of an Intel i7 CPU, an Nvidia 960 GPU, and a Xilinx Kintex Ultra-scale FPGA. Comparing to the benchmark (a C++ based implementation), we are able to accelerate the ESS simulator by more than 80x on the GPU and 25x with FPGA, with the same simulation accuracy (double precision floating point). We identified the implementation bottleneck on the specific platform, which is the memory bandwidth. This leads to our future work. One important future task is to investigate different hybrid computing platforms of different vendors, considering computation capability, memory bandwidth, as well as design software. Moreover, different data types will be examined, including fixed-point, double/single-precision floating point, or custom floating point.