DIGITAL GAIN ERROR CORRECTION TECHNIQUE FOR 8-BIT PIPELINE ADC
An analog-to-digital converter (ADC) is a link between the analog and digital domains and plays a vital role in modern mixed signal processing systems. There are several architectures, for example ﬂash ADCs, pipeline ADCs, sigma delta ADCs,successive approximation (SAR) ADCs and time interleaved ADCs. Among the various architectures, the pipeline ADC oﬀers a favorable trade-oﬀ between speed,power consumption, resolution, and design eﬀort. The commonly used applications of pipeline ADCs include high quality video systems, radio base stations,Ethernet, cable modems and high performance digital communication systems.Unfortunately, static errors like comparators oﬀset errors, capacitors mismatch errors and gain errors degrade the performance of the pipeline ADC. Hence, there is need for accuracy enhancement techniques. The conventional way to overcome these mentioned errors is to calibrate the pipeline ADC after fabrication, the so-called post fabrication calibration techniques. But environmental changes like temperature and device aging necessitates the recalibration after regular intervals of time, resulting in a loss of time and money. A lot of eﬀort can be saved if the digital outputs of the pipeline ADC can be used for the estimation and correctionof these errors, further classiﬁed as foreground and background techniques. In this thesis work, an algorithm is proposed that can estimate 10% inter stage gain errors in pipeline ADC without any need for a special calibration signal. The eﬃciency of the proposed algorithm is investigated on an 8-bit pipeline ADC architecture.The ﬁrst seven stages are implemented using the 1.5-bit/stage architecture whilethe last stage is a one-bit ﬂash ADC. The ADC and error correction algorithms simulated in Matlab and the signal to noise and distortion ratio (SNDR) is calculated to evaluate its eﬃciency.
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