Characterization, Clock Tree Synthesis and Power Grid Dimensioning in SiLago Framework

Abstract: A hardware design methodology or platform is complete if it has the capabilities to successfully implement clock tree, predict the power consumption for cases like best and worst Parasitic Interconnect Corners (RC Corners), supply power to every standard cell, etc.This thesis has tried to solve the three unsolved engineering problems in SiLago design. First, power characterization of the flat design which was designed using the SiLago methodology. Second, designing a hierarchical clock tree and harden it inside the SiLago logic. Third, dimensioning hierarchical power grids. Out of these, clock tree illustrates some interesting characteristics as it is programmable and predictable.The tools used for digital designing are Cadence Innovus, Synopsys Design Vision, and Mentor Graphics Questasim. These are very sophisticated tools and widely accepted in industries as well as in academia.The work done in this thesis has enabled SiLago platform one step forward toward its fruition.