Integrated Circuit Yield Enhancement - Redundant Multi Core DSP Cluster

University essay from Chalmers tekniska högskola/Institutionen för data- och informationsteknik

Author: Mikael Andersson; [2010]

Keywords: ;

Abstract: The manufacturing of integrated circuits is not a perfect fault-free process. The constantdownscaling of integrated circuits requiring higher accuracy each generation also allows thedesigner to fit more transistors in the same area. From a manufacturing point of view, thisdownscaling introduces additional possible sources of error, which forces a constant struggleto keep the yield or ratio of successfully manufactured chips high enough to be profitable. Themanufacturing success ratio, or yield, is a major component of what determines the time andmaterial cost it takes to manufacture an integrated circuit.

To increase yield a common approach is to add redundant or spare parts to the systemrequiring only enough of them to work.

Redundancy has long been a common concept in memories. For random logic blocks, theoverhead cost has been too large to be reasonable. But for multi core systems, with severalinstances of the same logic block, the situation is starting to resemble the case of a memory.

The manufacturing yield can be predicted by statistical models. Such models may consist ofanalytical expressions based on very low level information such as the exact layout features ofevery transistor and wire of the entire chip. However the addition of a spare core for a multicore cluster is an architectural decision that has to be made in the early stages of the designwhere low level details are not readily available.

The modeling approach taken in this project uses a collection of simplified models previouslyused for yield calculations for memories. The model results in estimates of the yield beforeand after the addition of redundant cores. The input parameters to the model are based on gatecounts and global routing estimates of an early floor plan together with information about themanufacturing process in the form a fault density.

When sources of defects are found and suppressed, the yield ramps up. The yield modelpresented here also shows the effect the redundancy has on the yield ramp, pushing it towardsan earlier volume production date, potentially decreasing the product time to market.