Study of Scalable Architectures on FPGA for Space Data Processors

Abstract: Spacecrafts are notably complex systems designed and constructed in multidisciplinary teams. The on-board computer of a spacecraft is part of the on-board data systems in charge of the on-board processing and handling of payload data collected from the instruments, which require high-performance radiationhardened-by-design (RHBD) processing devices. Over the last decades, the demand of high-performance systems used as on-board payload data processing systems has been increasing steadily due to new mission requirements, such as flexibility, faster development time, and new applications. At the same time, this user trend creates a need for higher performance components operating in radiation environments. The architecture proposed in this thesis is motivated by the results of recent activities supported by the European Space Agency (ESA) in the fields of Network-on-Chips (NoC) and floating-point VLIW Digital Signal Processors (DSPs). This architecture aims to study scaling aspects of VLIW-enable DSP SoC designs using FPGAs. The project shall perform the necessary pre-study activities required for the SoC design, such as synthesis of the IPs on the target FPGA technology. Lastly, using several DSPs for processing, a LEON3 processor for control, and several components from the GRLIB IP Library, the architecture implemented provides the user an with early version of a platform for further software development on multi-DSP platforms. Also, this architecture consists on a quad-core DSP system, providing a high-performance platform.