One Million-Point FFT

Abstract: The goal of this thesis has been to implement a hardware architecture for FPGA that calculates the fast Fourier transform (FFT) of a signal using one million samples. The FFT has been designed using a single-delay feedback architecture withrotators and butterflies, including a three-stage rotator with one million rotation angles. The design has been implemented onto a single FPGA and has a throughput of 233 Msamples/s. The calculated FFT has high accuracy with a signal to quantization noise ratio (SQNR) of 95.6 dB.