Characterization of FPGA-based Arbiter Physical Unclonable Functions

Abstract: The security of service, confidential data, and intellectual property are threatened by physical attacks, which usually include reading and tampering the data. In many cases, attackers can have access to the tools and equipment that can be used to read the memory or corrupt it, either by invasive or non-invasive means. The secret keys used by cryptographic algorithms are usually stored in a memory. Physical unclonable functions (PUFs) are promising to deal with such vulnerabilities since, in the case of PUFs, the keys are generated only when required and do not need to be stored on a powered-off chip. PUFs use the inherent variations in the manufacturing process to generate chip-unique output sequences (response) to a query (challenge). These variations are random, device-unique, hard to replicate even by the same manufacturer using identical process, equipment and settings, and supposed to be static, making the PUF an ideal candidate for generation of cryptographic keys. This thesis work focuses on a delay-based PUF called arbiter PUF. It utilizes the intrinsic propagation delay differences of two symmetrical paths. In this work, an arbiter PUF implemented in Altera FPGA has been evaluated. The implementation includes Verilog HDL coding, placement and routing, and the communication methods between PC and FPGAs to make testing more efficient. The experimental results were analyzed based on three criteria, reliability, uniqueness, and uniformity. Experimental results show that the arbiter PUF is reliable with respect to temperature variations, although the bit error rate increases as the temperature difference becomes larger. Results also reveal that the uniqueness of the PUFs on each FPGA device is particularly low but on the other hand, the proportions of different response bits are uniform after symmetric routing is performed.