Implementation and Evaluation of Espresso Stream Cipher in 65nm CMOS
Abstract: With the upcoming 5G networks and expected growth of the Internet of Things (IoT), the demand for fast and reliable encryption algorithms will increase. As many systems might be time critical and run on internal power sources, the algorithms must be small, fast, energy efficient and have low latency. A new stream cipher called Espresso has been proposed to answer these demands, optimizing for several parameters unlike other stream ciphers such as Trivium and Grain. Espresso has previously been compared to the industry standard, Advanced Encryption Standard (AES), in a FPGA implementation and has shown promising results in terms of power usage but further testing needs to be done to gain knowledge about the ciphers characteristics. The purpose of this thesis is to implement and evaluate Espresso in 65nm CMOS technology and compare it to AES. Espresso is implemented in VHDL in several configurations, optimizing for size and latency. The implementations are then compared to AES is in terms of area, throughput, energy efficiency and latency through simulation. This is done using the UMC 65nm CMOS library and Synopsys Design Vision. It is found that Espresso, implemented with 1 bit sequential loading of the key and IV, is 18.2x smaller, 3.2x faster, uses 9.4x less power and has 1.5x less latency than AES. When implemented with full parallel loading, Espresso still is 13.6x smaller, 3.2x faster, draws 7.1x less power while also having 3.2x lower latency than AES. Espressos energy efficiency can further be improved by applying low- power techniques although some techniques, like clock gating and power gating, have limited applicability due to of the nature of stream ciphers.
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