Design and Optimization of an Analog Front-End for Biomedical Applications

Abstract: The state-of-the-art analog front-end of implantable biosensors is the class of current-mirror-based circuits. Despite their superior noise performance, power consumption and area, they suffer from systematic and random errors causing offset, gain and linearity error in reading out the sensor data. In the first part of this thesis, a new analog front-end is proposed to eliminate the systematic error. The proposed topology is able to accurately copy the sensor current which will be converted into the proportional voltage for further processing. Additionally, a theoretical discussion regarding the functionality of the proposed topology is given and a thorough study on the effect of random error sources is carried out. In the second part of this thesis, in order to optimize the design of the proposed analog front-end, an optimization algorithm is proposed. The proposed optimization algorithm takes advantage of a modified Imperialist Competitive Algorithm. The original imperialist competitive algorithm shows a low search ability in high-dimensional search spaces which is the case in optimization of analog circuits. A thorough comparison between the original imperialist competitive algorithm, the proposed algorithm and genetic algorithm as a reference is carried out. It will be revealed that the proposed algorithm is capable of exploring the cost space more efficiently than the other two algorithms, thereby resulting in better trade-offs between design objectives to reach higher cost values. Furthermore, according to the mathematical benchmarks, the proposed algorithm is more than 1.5 times faster than the other algorithms in finding the global minimum, which is essential in simulation-based optimization procedures. The proposed optimization algorithm is used to design the proposed analog front-end. The results show an average of 25.8 times higher FoM when designed with the optimization algorithm as opposed to traditional design. The design and simulation is carried out in a commercial 150nm CMOS process. The optimally-designed analog front-end shows a highly-linear highly-accurate performance in a low-noise condition, while consuming only 32μW.