Modeling Shared Memory Access in a SystemC/TLM-based Many-core Virtual Platform

University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

Author: Tony Lundgren; [2019]

Keywords: ;

Abstract: The market for embedded devices is fast paced and is growing quickly. To be competitive, time-to-market is important for new products. To shorten the time it takes to release new products, hardware simulators in the form of virtual platforms are developed to allow software development to start before hardware is available. Virtual platforms model hardware at a high abstraction level, ideally a virtual platform should be as simple as possible, with functionally correct models of the hardware, but to allow complex software to run some timing must be modeled as well. The more timing that is modeled the more complicated the virtual platform becomes. This can make the virtual platform more prone to bugs. It can result in software that is sensitive to changes in the virtual platform if software is developed depending on the modeled timing. Modeling too much timing can also make the virtual platform too slow to run large programs. This thesis investigates how accesses to shared memory resources are modeled in a virtual platform using SystemC, compared to the the many-core system it emulates. This SystemC simulation uses many SystemC processes, and frequently switch between the processes. A tool to visualize these switches between SystemC processes is developed. Changes are implemented to reduce context switching between SystemC processes. Reducing context switching is good because each switch has some penalty in performance because of the overhead invoking the SystemC kernel, fewer context switches also mean SystemC processes are synchronizing less often which makes it possible to gain performance by running multiple SystemC processes in parallel. These changes are evaluated running production software tests. The results show that the changes reduce context switching by 94% for one test program, and reduce the total run time for the same program by 16% on average. Though one of 159 software tests fail with the changes, the simplifications of the virtual platform in this thesis show the potential benefits of a simpler simulation model.

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