VHDL Implementation of a Fast Adder Tree
This thesis discusses the design and implementation of a VHDL generator for Wallace tree with (3:2) counter modules and (2:2) counter modules to solve fast addition problem.
The basic research has been carried out by MATLAB programming environment and automatic generation of VHDL file based on the result obtained from MATLAB simulation. MODELSIM has been used for compilation and simulation of the VHDL file.
AT THIS PAGE YOU CAN DOWNLOAD THE WHOLE ESSAY. (follow the link to the next page)