Development of a new verification environment for a GPU hardware block using the Universal Verification Methodology

University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

Author: Niklas Karlsson; [2020]

Keywords: Technology and Engineering;

Abstract: The invention of the integrated circuit is a key milestone in the history of electronic circuits. Since its introduction the number of components on a chip have increased rapidly, making them more powerful and able to perform complex operations, but it has also changed the design process. Today different parts of a chip can be developed separately as Intellectual Property (IP) and then put together to form the final system. Over the last years making sure that the design follows the specification, also known as functional verification, have become a key part of the development life cycle. Finding bugs early is crucial for keeping cost down and achieving time-to-market requirements. This means that as the complexity of the design continues to increase, the time needed to thoroughly verify it cannot follow the same line of increment. This has pushed engineers to come up with new tools and methodologies to improve the verification process. The Universal Verification Methodology (UVM) is created by Accellera together with experts from electronic design automation vendors Synopsys, Mentor and Cadence. Its emphasis is on improving the development of verification environments by increasing interoperability and making it easier to reuse verification components. This project will develop a new verification environment verification environment according to the Universal Verification Methodology to investigate how it can be implemented when separately developed blocks are verified together. A hardware block with sub-components from a Graphics Processing Unit (GPU) will be used and the methodology will be analysed based on how it affects the structure and performance of the verification environment. The dissertation will result in a new implemented verification environment along with guidelines on how to possibly improve block-integrating verification in general and verification of graphics processor specifically.

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