Implementation of a Hardware Coordinate Wise Descend Algorithm with Maximum Likelihood Estimator for Use in mMTC Activity Detection
Abstract: In this work, a coordinate wise descent algorithm is implemented which serves the purpose of estimating active users in a base station/client wireless communication setup. The implemented algorithm utilizes the sporadic nature of users, which is believed to be the norm with 5G Massive MIMO and Internet of Things, meaning that only a subset of all users are active simultaneously at any given time. This work attempts to estimate the viability of a direct algorithm implementation to test if the performance requirements can be satisfied or if a more sophisticated implementation, such as a parallelized version, needs to be created.The result is an isomorphic ASIC implementation made in a 28 nm FD-SOI process, with proper internal word lengths extracted through simulation. Some techniques to lessen the burden on hardware without losing performance is presented which helps reduce area and increase speed of the implementation. Finally, a parallelized version of the algorithm is proposed, if one should desire to explore an implementation with higher system throughput, at almost no furtherexpense of user estimation error.
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