Debug Interface for 56000 DSP
The scope for this thesis was to design a debug interface for a DSP (digital signal processor). The DSP is a research version of a Motorola 56000 that is designed for a project on asynchronous processor and for use in education.
The DSP and debug interface are controlled via a standard PC with RS232 interface equipped with Linux operation system.
In the project 4 blocks has been designed:
The first block can set the DSP core in debug mode or run mode. The second block sends a debug instruction to the DSP core, these debug instructions were prerequisite to the project. The third block enable read and write connection to the memory buses between the DSP core and the three memory blocks. The forth block can override the control signals to the memories from the DSP core.
The project also uses an UART for interpreting and sending control signals and data between the different blocks and the computer.
A text terminal program for Linux has also been programmed for handling the PC side communication.
The hardware has been constructed and tested together with a dummy DSP core and dummy memories, but it has not been tested together with the live DSP core.
The Linux program has been tested the same way and seems to do what it's supposed to, though it leaves a lot work to be easy to handle.
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