FPGA implementation of an sEMG classifier

Abstract: This master’s thesis discusses the implementation of a convolutional neural network on a Field Programmable Gate Array (FPGA). It deals with implementation be describing a tool chain, starting with the designing of a model in Keras, transforming the model to Hardware Descriptive Language, and finally implementing it on an FPGA. Performance on three different scales of the same model topology are compared, in the following terms: accuracy, timing and power consumption. Findings show that timing is within acceptable ranges, with limitations lying in model capacity, and power consumption. Furthermore, the specific model is compared with a similar topology. Finally, suggestions for future attempts are proposed, suggesting new layer types.