System Level Modeling and Verification of All-digital Phase-locked Loop

Abstract: In wirelesscommunication systems, a local oscillator (LO) aims at demodulating radio-frequency signals into baseband signals. The performance of these signals determines the quality of communications which is highly affected by the phase accuracy of local oscillators. Therefore, evaluating jitter/phase noise should be an essential part when designing wireless communication systems. Typically, LO is achieved by traditional analog PLL. These prototypes have several drawbacks including low integration, narrow bandwidth and high phase noise. With the development of digital techniques, approaches towards an All-digital Phase-Locked Loop have been forwarded against the traditional analogy type. The thesis mainly deals with the modeling and verification of an All-digital Phase-Locked Loop concerning its architecture, functionality and phase noise modeling and analysis. It starts with a comparison of current frequency synthesizers including direct analog/digital synthesis and indirect synthesis using PLL/ADPLL. The advantage and analogy of ADPLL versus traditional PLL in radio-frequency applications has been discussed. In order to gain overall understanding of ADPLL, a behavioral theory in both time and phase domain has been conducted in detail. Analysis shows that the restrictive factors of proposed ADPLL lie in TDC and DCO phase noise. It is also proved that the bandwidth and settling time of ADPLL is determined by proportional and integrating parameter of loop filter. Upon the completion of ADPLL theory analysis, a model based on simulink has been put forward. The phase noise level of TDC is specified and mode switch is implemented in order to improve the speed of ADPLL. The reason for choosing 2nd-order MASH-1-1 type ߢ modulator is briefly discussed. The phase noise of DCO is generated in time-domain using filtered Gaussian distribution and the free-running DCO achieves -20dB/dec spectrumfrom 10Hz to 500kHz. The results verified the feasibility of proposed ADPLL by achieving -50dBc/Hz in-band noise. Other results including howfractional precision, SDMclock and precision contributed to ADPLL phase noise has been presented. A tradeoff between phase noise shaping quality and settling time was evaluated. Ultimately, global parameters setup for the fulfillment of best performance is demonstrated.