Acceleration of Pedestrian Detection System using Hardware-Software Co-design

Abstract: Object detection technologies, represented by face detection system which has been studied for a long time, have developed recently because of the development of technologies of high performance computing and pattern recognition technique. Especially, pedestrian detection system has gathered attention recently, and it will be applied to an automobile safety system and monitoring camera system. While many research of acceleration and improvement of detecting accuracy have been published, system design as distributed system is also required. While a centralized computing system which sends raw image data to central processing node presses networks, distributed system which operates some calculation before sending data to the network decreases the total amount of data volume. When we take account of using environment of pedestrian detection system, user flexibility is also important criteria. Pedestrian detection system should be set some parameters such as detecting window size, slide width of window and operating speed depending on each using environment. When you implement the whole system on an FPGA, you will lose flexibility of the system. Hardware-Software Co-design enables to enhance flexibility. Thinking of demands mentioned in above, this thesis aims acceleration of pedestrian detection system using Hardware-Software Co-design. In the implementation, our system adopts HOG (Histogram of Oriented Gradients) feature value and Real Adaboost as a classification algorithm. Also, our system aim data reduction without decrease of detecting accuracy, design as distributed system by implement on a single FPGA, and enhancement of flexibility using Hardware-Software Co-design. HOG feature data is reduced by segmenting to 6bit after converting HOG feature value from floating-point number to fixed-point number. In addition, output of classifier by Real Adaboost algorithm is calculated by high-precision in advance, and these values are stored to ROM on the FPGA. This enables to reduce data volume without much loss of detecting accuracy. As a result, whole pedestrian detection system is implemented on a single FPGA board, and it accelerated in 3.22 faster than software only operation. In addition, feature data is reduced by 93.5% without much loss of detecting accuracy. Enhancement of flexibility using Hardware-Software Co-design also accomplished with ZedBoard FPGA and ARM Coretex-A9 processor on the board.