Fabrication and Characterization of Quantum-well Field Effect Transistor

Abstract: The project aims to optimize the design and fabrication of InGaAs quantum-well field-effect transistor (QW-FET) by investigating transfer and output characteristics of the QW-FET. This work found a lower source/drain contact resistance solution starting with fabricating micrometer-level gate length transistors. It is a multiple-layer design, n-type InGaAs and n-type InP over channel. The stack of metal-oxide-semiconductor (MOS) was studied as well, and the lower subthreshold swing (SS) indicated that oxide layer contact with channel is a better way to control gate electrostatic. To precise the data (contact resistance, sheet resistance and electron mobility) derived from the ON-state resistance and transconductance in transistors, short-gate QW-FET, less than 1 micron, processed using electron-beam lithography technology. Although leakage occurred, it is feasible to attain a promising transistor with high electron mobility and low contact resistance. Moreover, Post Metallization Annealing (PMA) and measurement temperature impacts on transistor performance were also assessed in this work. The evidence shows that the performance parameters of transistors were upgraded after PMA 350℃ in N2/H2 for five minutes. The reason is related to a lower density of defect at the interface of channel and high-κ layer after annealing, and thus the chances of electrons scattering by the Coulomb are reduced. However, the resistance results of transmission line model (TLM) did not obviously decrease. By testing transistors at 13K, doubled electron mobility was found, and the dropping of SS also indicated a boost of gate electrostatic control at low temperature.