Spice Circuit Reduction for Speeding up Simulation and Verification

Abstract: The focus of this work has been to implement a generic netlist reduction engine to speed up circuit simulations. The netlist reduction techniques are further optimized for Static Random-Access Memory (SRAM), wherein we exploit the repetitive pattern of the circuit. There are many driving factors for developing a netlist reduction engine for SRAM simulations. In today's System on Chip (SoC), SRAM sizes are in megabyte ranges to support ever-increasing demands for features. The increasing size of SRAM makes it one of the biggest contributors of power consumption and area of a SoC. Many of today's state-of-the-art SoCs have on average more than 50% area and power consumption due to SRAMs. Hence it is very crucial to run full simulations of SRAM to check functionality, timing and power numbers. Unfortunately, due to the huge size of SRAM, it is unfeasible to simulate the whole SRAM, since it would take in the order of months to perform simulations. Also, a typical SRAM needs to be run for different corners, which is performed by Monte Carlo simulations, which is even more computationally intensive. Tackling these issues is the key focus of this thesis. We perform this by exploiting the iterative nature of the SRAM circuit. The design is implemented in Python and verified on Xenergic's latest SRAM by using Cadence simulation tools. The reduction engine has shown to provide a speed up of around 95% (using Spectre simulator) for a 4kb SRAM. Timing deviations of simulation results between the original SRAM netlist and a reduced netlist are below 5%. Furthermore, there is no difference when it comes to SRAM functionality via the digital interface. In addition, time for the whole reduction process is far less than saved simulation time for a large scale circuit.