Adder Minimization and Retiming in Parallel FIR-Filters : Targeting Power Consumption in ASICs

Abstract: Parallelized implementations of FIR-filters are often used to meet throughput and power requirements. The most common methods to optimize coefficient multiplication in FIR-filters are developed for single rate filters, thus the added redundancy of parallel implementations cannot be utilized in the optimization. In this work optimization methods utilizing the redundancy of parallel filter implementations are evaluated for a set of low-pass and interpolation filters. Results show that the proposed methods offer parallelization with less than linear increases in hardware for several evaluated filters with up to 47% reduction in adder count compared to conventional methods. Furthermore, an optimization algorithm for retiming of algorithmic delays is evaluated both with and without pipelining. Synthesis results show that the retiming algorithm can reduce the power consumption with up to 48% without added latency for high throughput applications.