Loss-less on-chip test response compression for diagnosis and debug in volume production of system-on-chip
Abstract: The technical evolution during the past decade have escalated the use of electronic devices, which are more common today than ever before. The market is still growing rapidly and will continue to do so. The reason for this is the increased demand for devices with integrated circuits. In addition to the increased volume of production, the chips are also becoming more complex which is also reflected in the requirements of the chip design process. An advanced chip that combines several different hardware modules (cores) to form a complete system is called a System-on-Chip (SoC). It is of great importance that these chips work according to expectation, although it can be difficult to guarantee. The purpose of SoC testing is to verify correct behaviour as well as for diagnosis and debug. Complex systems lead to more and bigger tests which lead to increased test data volume and test time. This results in a higher test cost and many methods are proposed to remedy this situation. This report proposes a method that minimises fail result data with a real-time compression component embedded on the chip. The compressed fail results can be saved on-chip and retrieved when needed instead of during the test. Furthermore this method will facilitate debug and diagnosis of SoCs. A mask buffer is used to give the opportunity of choosing exactly which cycles, pins or bits that are relevant. All other result bits are masked and ignored. The results are satisfying, the data is compressed to a much smaller size which is easier to store on-chip. The method is simple, fast and loss-less.
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