Firmware Design and Implementation for a 14-bit Analog-to-Digital Converter to be used in the PANDA Experiment
Development of the VHDL firmware for a high-speed Analogue to Digital Converter (ADC) is the focus of this paper, including writing, debug- ging and evaluation of said firmware. The finished version of the firmware is able to correctly convert analogue signals received by the ADC into their digital representations. This result requires fully functional Phase Locked Loop, Clock Manager, ADC Wire/SERDES and ADC components, as well as functioning Phase Delay and Bitslip algorithms, all of which are discussed in this paper.
AT THIS PAGE YOU CAN DOWNLOAD THE WHOLE ESSAY. (follow the link to the next page)