Low Power Current Mode Delta-SigmaADC using Ring Oscillator basedQuantizer

Abstract: Low power ADCs have wide range of applications, from battery operated systems like biomedical devices to on chip power measurement systems. A more digital implementation is also desirable to take advantage of the technology scaling in digital CMOS technologies. This thesis explores the idea of a low power continuous time Delta-Sigma ADC using current mode signaling. It achieves a second order noise shaping by using a first order current filter, a digital dierence block and a current controlled ring oscillator. This type of ADC has a mostly digital implementation, as the main analog blocks are the current-mode filter and two op-amps which are used for biasing.The behavioral level ADC is implemented in VerilogA and the transistor level ADC is deisgned in CADENCE using UMC 180nm process. MonteCarlo simulations are also performed to ensure the proper operation of the current-mode filter in presence of mismatches, as log-domain filters are very sensitive to transistors mismatches. The ADC performance obtained from transistor level simulation is 7:3 Effective Number of Bits (ENOB) over 30KHz bandwidth and 5.3W power consumption.