A design of a 100 MS/s, 8-bit Pipelined ADC in CMOS

Abstract: The thesis focuses on designing and simulating an 8-bit high-speed fully differential pipelined Analog to Digital Converter (ADC) in the 65nm Complementary Metal-Oxide-Semiconductor (CMOS) technology by using the software Cadence Virtuoso. The aim is to increase the operation speed of the ADC for communication systems without reducing the performance, in the meantime, the low power consumption and the low complexity should also be required when considering future implementation. The ADC works on 200mV to 800mV with 1.2V supply voltage and consists of six 1.5-bit stages, one 2-bit stage, and a series of digital correction circuits in the end. A Flash ADC, and a Multiplying Digital to Analogue Converter (MDAC) have been designed for each 1.5-bit stage, while the MDAC is not included in the 2-bit stage. SHA is designed at the beginning but not included in the final schematic since the sampling function is included in the MADC and the Flash ADC. The design also includes a bootstrapped switch to increase the linearity of the switches, a dynamic latch comparator to increase the speed of the Flash ADC, and a fully differential Operational Amplifier (OpAmp) to reduce the impact of the external noise, decrease the second-order harmonic distortion and increase the dynamic range. Simulation results illustrate the SNDR reaches 48.64dB when the sampling rate is 100MHz, and it remains 47.3dB when the sampling rate increases to 200MHz.