Design and Acceleration of Linear Integer System Solver on Programmable SoC
Abstract: A simple solver for linear integer systems is designed and accelerated on aCycloneV SoC chip that contains Cortex-A based MCU, programmable FPGA, andinter-connect bridges. The solver is designed based on the Gaussian Elimination method, where a system coefficient matric is converted to a Row-Echelon matrix and performing back Back-Substitution to solve system variables. The matrix conversion is implemented in the FPGA with serial and parallel architectures, where the processing of two equations is performed using single and multiple reducer modules. In comparison with the software-based solver, the solver with hardware based-based matrix conversion modules are faster by at least 75% despite very high MCU clock and data transfer overhead between the subsystems.
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