A Synthesizable VHDL Behavioral Model of A DSP On Chip Emulation Unit
This thesis describes the VHDL behavioral model design of a DSP On Chip Emulation Unit. The prototype of this design is the OnCE port of the Motorola DSP56002.
Capabilities of this On Chip Emulation Unit are accessible through four pins, which allows the user to step through a program, to set the breakpoint that stop program execution at a specific address, and to examine the contents of registers, memory, and pipeline information. The detailed design that includes input/output signals and sub blocks is presented in this thesis.
The user will interact with the DSP through a GUI on the host computer via the RS232 port. An interface between the RS232 and On Chip Emulation Unit is therefore designed as well.
The functionality is designed to be same as described by Motorola and it is verified by a test bench. The writing of the test bench, test sequence and results is presented also.
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