FPGA-Based Acceleration of LTE Protocol Decoding
Abstract: This work investigates the possibility to accelerate a procedure in 4G/LTE systems, known as control channel analysis. The aim is to perform the procedure in real-time on cheap and accessible hardware.An LTE decoder implemented in software is modified to perform the procedure.The modified software is analyzed and profiled. The most time-consuming decoding steps are identified and implemented in hardware description language.The results show an acceleration of the most time-consuming steps of almost 50 times faster compared to implementation in software only. Furthermore, the resource utilization of the hardware design scales linearly with respect to faster decode time, if necessary the acceleration can be increased. However, the results from the profiling and time measurements of the software show that the time requirement is violated by other decoding steps.The thesis concludes that an acceleration in hardware of the most time-consuming steps is possible. However, to satisfy the time requirement further decode steps are required to be accelerated and/or a faster processor can be used.
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