NoC for Versatile Micro-Code Programmable Multi-Core Processor Targeting Convolutional Neural Networks

Abstract: This thesis investigates building a network-on-chip for a multi-core chip computing convolutional neural networks (CNNs) using Imsys processors in a tree architecture. The division of work on a multi-core chip is investigated. Key patterns of communication are identified and three designs allowing for increasingly more advanced communication patterns are implemented in VHDL. Each design is evaluated on throughput, latency and design size by running tests on the communication patterns in simulation. A relation between design size and throughput is shown, though the throughput decreases for different communication patterns when resorting to networks with lower design size. Depending on what layers are present in a CNN of interest, a network can be chosen with as small design size as possible while still achieving desired results. Aspects such as implementation and usage difficulties and energy consumption are discussed in the thesis as well; however, only on a theoretical level.