Analyzing and implementation of compression algorithms in an FPGA

Abstract: The thesis is performed at ÅF AB in Stockholm. One of the development projects needed a compression algorithm. The work has been done in two major stages. Background theory was compiled and evaluated with respect to the suitability for FPGA implementation. One implementation phase were also done where the algorithms that was suitable was implemented. The system the algorithm was integrated into was composed of a Xilinx Virtex 5 FPGA platform integrated into a system developed at ÅF AB. The development was mainly done in VHDL, other programming languages such as Matlab and C++ was also used. A testbench was constructed to evaluate the performance of the algorithms with respect to the ability to compress data in a test file. This test showed that the Run length encoding was most suited for the task. The result of this test was however not the only source of information for a choice of algorithm. Due to a privacy agreement some variables is not included in the report. The design constructed was designed to act as a foundation for future thesis work within ÅF AB.