Ring amplifiers for high speed pipeline assisted SAR ADCs
Abstract: This thesis contains a review of published ring amplifier topologies. It is suggested to split the input stage of the ring amplifier into two. In this way, a robust ring amplifier can be designed without stacking the transistors in the second stage of the ring amplifier, boosting its speed properties. The split input stage can also be used to design a fully differential bias enhanced ring amplifier, boosting the ring amplifiers settling properties at the cost of lower gain. A figure of merit for the ring amplifiers is suggested. The advantages and disadvantages of using ring amplifiers in pipeline assisted SAR ADC is discussed with regards to noise power, linearity, settling speed and PVT robustness. A figure of merit for ring amplifiers is suggested. A ring amplifier based pipeline assisted SAR ADC is implemented with some non-critical components realized using behavioral modelling. The implemented ADC reaches, SNR 58 dB, SFDR 71 dB, consuming 3.3 mW operating at 550 MHz. The performance of the pipelined SAR ADC is compared with an existing conventional SAR ADC. It is concluded that the ring amplifier is well suited for high speed pipeline assisted SAR ADCs from a noise, linearity and power perspective but it is somewhat limited by its relatively low settling speed.
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