HIGHLY CRITICAL GRAPHICS GENERATION ON A SYSTEM-ON-CHIP PLATFORM

Abstract: The critical applications domain stands today at the brink of a great divide. On one side, the deterministic and safe operational prerequisite of the system. On the other, an ever increasing demand for computational power and miniaturization. In some cases, the welfare of people hinge in the balance of these attributes. It is therefore vital that these system undergo strict and rigorous development and testing. Development has evolved a great deal with regards to computational power and miniaturization. So too has the development of deterministic and safely operational systems. However the combination of these two are a complex matter. A light in the dark might be seen in the Commercial Off The Shelf System-on-Chip, which offers great computational power in relation to its volume. This thesis’s objective is to investigate potential fault-detection methods applicable on commercial System-on-Chip. To determine applicability, multiple implementations have been made and tested. Results from which suggest that fault detection methods implemented on field programmable gate array are highly effective. However, not all worst case execution time analysis conducted in this thesis are deemed a success. A common-mode analysis is conducted which indicated that functions already present on the System-on-Chip, before implementation, negated the effect of common-cause failures under scrutiny in the analysis. The majority of the data gathered from state of the art, implementations and common-mode analysis conducted, indicate that commercial off the shelf multi-processor System-on-Chip platforms have great potential in safety critical systems.