Design and Implementation of Dynamic Flow Regulation for On-chip Networks

Abstract: In modern System-on-Chip systems, flow regulation can be used to integrate IP blocks into the system architecture, simultaneously guaranteeing Quality of Service and achieving cost-effective communication. However, static regulation with hard coded regulation policy lacks of flexibility to accommodate traffic flows with varying characteristics and patterns influenced by complex system behavior. Besides, static regulation may result in overly loose regulation in order to satisfy conflicting regulation requirements of different flows. To overcome the weaknesses of static regulation, in this thesis, we present a dynamic regulation mechanism that can self-adaptively make dynamic regulation decisions according to actual incoming traffic flows from master IP blocks. The whole dynamic regulation process is realized with a 3-stage closed-loop control mechanism: prediction, decision, and execution. Accordingly, predictor, director, and regulator are designed and implemented to fulfill the tasks of each control stage. We compare our approach with the static regulation scheme on the Nostrum Network-on-Chip with deflective routing. The experimental results show that, when regulating Markov Modulated Poisson Process traffic flows, our dynamic regulation scheme enjoys less interconnect delay and requires smaller interface buffers than the static regulation scheme, and therefore makes more effective use of the system interconnect with flexibility.