Vertical heterostructure III-V nanowire MOSFETs

Abstract: If cars had developed as fast as processors they would go at 470,000 mph, get 100,000 miles to the gallon, and cost 3 cents" claims Paul Ottelini, Intel CEO 2005-2013. This serves as a reminder of how fast the field of nanoelectronics is developing due to constant demand for faster and more energy efficient integrated circuits. The still ongoing electronics revolution was accelerated by the innovation of one simple and elegant device, namely the Si-based metal-oxide-semiconductor-field-effect-transisor MOSFET in 1959. The pillar of economic growth has since been based on downscaling the MOSFET and increasing the density of transistor per chip area. Downscaling of the transistor has favourably led to more efficient and faster devices. MOSFETs today are approaching sizes which only include few monolayers of atoms, basically dimensions of a few nanometer. Conventional electronics has thus been pushed into the quantum realm forcing future improvements to be based on innovation rather than simply downscaling. To win the battle against Heisenberg's uncertainty leading to leakage currents and various other effect due to reduced size, new 3d geometries has been introduced. Amongst these new geometries is the bottom up approach utilizing vertical nanowires. The vertical geometry also enables easier integration of alternative high mobility semiconductor materials on a Si substrate. A potential canditate for integration on Si is the III-V compound semiconductors due improvements in charge carrier transport capabilities. To further motivate a switch in transistor geometry the full infrastructure of devices need to be present, not only satisfying the logical domain. Therefore, in parallel to the digital branch, a wish for developing better analog RF-transistors is present. The requirements for an RF-transistor are quite different where stability and high frequency signal gain is of importance. In an RF circuit power dissipation can be sacrificed for increased performance, lending more room for new innovations. In this thesis the use of the vertical nanowire geometry for MOSFET is further investigated by implementing a III-V, InAs/InGaAs, graded heterostructure, inside the channel, optimized for increased stability and low resistance ohmic-contacts. A Si-substrate with grown III-V nanowires, on top of a InAs buffer layer, is provided and afterwards processed into a complete set of devices. The orientation of the grading is chosen with an abrupt junction from the InAs buffer layer to InGaAs slowly graded back to InAs at the top, by implementing 550 nm long nanowires. The measured DC-characteristics indicates a presence of the heterostructure due to good saturation, low output conductance g_d = 2 uS/um at V_ds = 0.5 V and V_gs = 0.5 V. Amplification and current does not reach intended values because of large access resistance, R_c = 1500 Ohm'um, with transconductance g_m,max = 280 uS/um. Good gate control is indicated with devices showcasing low sub-threshold swing SS down to 80 mV/dec. Motivation of introducing a heterostructure is clear due to higher breakdown and increased linearity but the choice of the grading orientation is not. Contact resistance is mostly originating from the source side, which means that there is large room for improvement by tweaking the process. The nanowires also had a tendency to collapse which decreased the performance. In other words the theory of implementing a heterostructure with abrupt junction for larger breakdown voltage and increased linearity is promising and cannot yet be disregarded.