Customization of Ibex RISC-V Processor Core
Abstract: Despite, the fact that we now have highly powerful and reliable CPU cores from System on Chip (SoC) Intellectual Property (IP) giants, the silicon industry is still leaning toward an efficient CPU core with an open-source Instruction Set Architecture (ISA) at the moment, where RISC-V has proven to be extremely successful. The aim to customize an open-source processor core, as described in our thesis subject, in order to find a cheaper alternative to high-priced CPU cores that can be tailored for specific applications is one of the key contribution of our thesis. It was anticipated that after customization, the Ibex core will perform better, so we employed three reference algorithms to customize the Ibex Core. With a custom constructed profiler, the goal was to discover the bottlenecks in the algorithm and build specific instructions to resolve them. Following that, we added custom instructions support to both software and hardware. Finally, after implementing custom instructions, hardware simulations were conducted and synthesis was performed. Post-customization results delivered on the expected promise by drastically reducing execution time while still maintaining a degree of hardware or gate count optimization.
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