Dynamic Load Generator: Synthesising dynamic hardware load characteristics

Abstract: In this thesis we proposed and tested a new method for creating synthetic workloads. Our method takes the dynamic behaviour into consideration, whereas previous studies only consider the static behaviour. This was done by recording performance monitor counters (PMC) events from a reference application. These events were then used to calculate the hardware load characteristics, in our case cache miss ratios, that were stored for each sample and used as input to a load regulator. A signalling application was then used together with a load regulator and a cache miss generator to tune the hardware characteristics until they were similar to those of the reference application. For each sample, the final parameters from the load regulator were stored in order to be able to simulate it. By simulating all samples with the same sampling period with which they were recorded, the dynamic behaviour of the reference application could be simulated. Measurements show that this was successful for L1 D$ miss ratio, but not for L1 I$ miss ratio and only to a small extent for L2 D$ miss ratio. We were also able to show that the total convergence time for the regulator could be reduced by using case-based reasoning to select the initial parameters from similar samples.