Implementation of 3GPP LTE QPP Interleaver for SiLago

Abstract: Modern wireless communication systems have seen an increased usage of various channel coding techniques to facilitate improved throughput and latency. Interleavers form an integral part of these coding techniques and play a critical role by making the communication more robust and resilient to noise and other interference. The ever increasing need for higher throughputs and lower latencies has made designers to pursue a more parallel design approach giving rise to parallel adaptations of these encoding/decoding techniques. A bulk of the modern telecommunication occurs over Wireless Wide Area Network (WWAN), commonly referred to as cellular networks. The 3rd Generation Partnership Project (3GPP), Long Term Evolution (LTE) develops and specifies the standards that are used in cellular communication. Their current most widely used "4G" standard employs Turbo coding techniques and a Quadratic Permutation Polynomial (QPP) interleaver. Silicon Large Grain Object or SiLago is a Coarse Grain Reconfigurable Fabric facilitating a modular approach towards electronics hardware development. The concept is similar to LEGO bricks, that is to have a library of hardened blocks (similar to Lego bricks) out of which systems of various types and functionalities can be built. This thesis investigates the state-of-the-art parallel interleavers and parallel interleaving techniques available for the 3GPP LTE QPP interleavers, and implements two interleaver designs, one for Radix 2 and another for Radix 4 decoding techniques. A physical synthesis is carried out in 28nm technology and the results in terms of power and area are reported.