Design Exploration of an FPGABased Face Detection ProcessingCore Utilizing High Level Synthesis

Abstract: Achieving object detection with computer vision places high demands on hardware resources and energy. This becomes apparent when considering that applications like surveillance, autonomous vehicles, mobile and other similar applications, employ embedded systems with even greater restrictions on processing power and memory bandwidth. Face detection is a vivid example of object detection. Not only is it fascinating and has many applications at the same time, it also does not limit the scope of the thesis to faces. The algorithm in use detects faces and other objects in the same manner, merely the required initial data differs between objects.This thesis explores the design space of object detection on a Field Programmable Gate Array (FPGA) by implementing a common face detection algorithm utilizing High Level Synthesis (HLS) and therefore leveraging the flexibility of FPGAs. The prerequisite of this exploration is fulfilled by implementing the algorithm in a synthesizable subset of ANSI-C and to measure performance and the demand of hardware resources. Different designs were synthesized for a Xilinx Artix-7 FPGA and compared to each other every step of the way.The result is a set of 12 different designs for custom FPGA accelerators with various performance and resource requirements. The design with the highest throughput balances two opposite design paradigms. One extreme is an accelerator with maximum hardware reuse, which results in a lower number of cores and maximum latency per processing core and the other with massive parallelization, which results in a higher number of cores and minimum latency per processing core. The balanced design achieves the maximum throughput while utilizing half of the limiting hardware resource.