Dynamic Reconfiguration using Crystalline Oxide Semiconductor Technology in a Multi-Context Field Programmable Gate Array

Abstract: Dynamically reconfigurable FPGAs was described in the 1990’s by Bolotski,Tau, DeHon and Trimberger. The idea was to expand the FPGA’sfunction space temporally instead of spatially, and in doing so allowing reuseof the FPGA’s functional resources in time, increasing the utilization rate of the functional resources. Many DPGA designs today are based on the "Time-Multiplexed FPGA" that Trim-berger et al. described in 1997 now more commonly called Multi-Context FPGA,in which memory bits are added to every configuration memory to create con-figuration contexts that the FPGA can switch between. The dominating memorytechnology used in FPGAs and DPGAs is SRAM; a volatile memory technologythat uses a relatively large area and also have an excessive power consumption. Because of the increase of configuration bits in DPGAs, the SRAM memory draw-backs imposes larger effects on its design.In recent years new memory technologies have been implemented in a broadrange of applications, out of which DPGAs are one. Among these technologies,implementation with crystalline IGZO FETs have been argued to overcome sev-eral of the earlier mentioned drawbacks in a DPGA. The memory technology isbased on a hybrid-process of CMOS and crystalline-IGZO, with IGZO materialstacked on top of the CMOS to save area; further, it has an extremely low off-statepower which reduces off-state leakage and is used to create small, non-volatilememory cells. In this thesis a way to enable dynamic reconfiguration in a CAAC-IGZO-based MC-FPGA is presented. A routing switch is presented and implemented to solvea problem in a reference design relating to boosting on the routing switchs’ con-figuration memories. The proposed routing switch is non-volatile and can reducearea by about 38% , and increase performance by 37% at a driving voltage of 1.5Vcompared to a SRAM-based routing switch.