Case study on Universal Verification Methodology(UVM) SystemC testbench for RTL verification

University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

Author: Kevin Skaria Chacko; [2019]

Keywords: Technology and Engineering;

Abstract: This Master’s thesis aims to conduct a case study on using Universal Verification Methodology (UVM) in SystemC for Register-Transfer Level (RTL) verification. Verification of ASICs is very important nowadays especially in terms of production costs, time to market and the sustainability of products. As Moore’s Law is in motion, verification gets large, complex, and time-consuming. Re-usability and simulation performance of testbenches are key areas for improvement. Accellera Systems Initiative, a standard organization that supports user and vendor standards in the field of EDA and ICs has released UVM in SystemC as a Beta version. Since SystemVerilog UVM testbenches have been around in industries for several years in different performance optimized versions, one of these versions is implemented in UVM SystemC to study if the same optimizations are possible. This will also enable to have a common language platform for SystemC Register-Transfer Level (RTL) and RTL testbench development. In order to simulate two different hardware modeling languages in an EDA simulator, 3 different methods of interfacing UVM SystemC with SystemVerilog RTL have been explored: UVM-Multi Language (ML), Beta over Legacy (BoL), and Standard Co-Emulation Interface(SCE-MI). Based on simplicity and simulation time the oL interface has been characterized for a better option. Moreover, knowing the relationship of SystemC simulation time with timing accuracy, a performance comparison with SystemVerilog UVM has helped to understand the bottleneck of SystemC testbench with cycle-accurate interfaces as compared to SystemVerilog interfaces where the simulator tool perform optimizations in context switching. From the results of the performance comparison, this study proposes a direction in using a hybrid testbench model where the stimulus and response data parts of the testbench are still in SystemC TLM whereas the cycle accurate interfaces with the RTL are in SystemVerilog.

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