Investigating DRAM bank partitioning
Abstract: We have investigated the page coloring technique bank partitioning and if it can be applied on commercial hardware platforms to reduce execution time jitter for specific tasks. We have also investigated how to alter execution times using bank partitioning. Unpredictable latency created by execution time jitter is a problem in real-time computing on commercial hardware platforms. We have run experiments that try to prove that the bank partitioning method we use alters the execution time and that thrashing occurs in the main memory if we run multiple instances of a workload. We receive significant changes in execution times when using bank partitioning and we can determine that thrashing occurs. However, due to the lack of the ability to measure the hardware performance counter for row buffer misses, we cannot determine if thrashing occurs in the main memory level. Since we cannot determine when, or if thrashing occurs in the main memory we find that we cannot reduce execution time jitter on the two systems that we have tested using bank partitioning on. We also find that execution times of specific tasks can be altered by reducing the number of bank bins associated with the specific task. The execution time of the task is increased if we reduce the number of bins associated with it.
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