D-band Power Amplifiers in Vertical InGaAs Nanowire MOSFET Technology for 100 Gbps Wireless Communication

Abstract: Two different topologies of power amplifiers (PAs) are designed in the frequency range 130-174.8 GHz for use in backhaul transmitters. These are the pseudo-differential common source (PDCS) and the single-ended stacked amplifier topologies. The PAs are designed in Cadence AWR design environment with virtual source models, implemented in Verilog-A, of InGaAs nanowire transistors using a 20 nm gate length. The results are compared amongst each other as well as with other state-of-the-art PAs. The PDCS PA achieves a simulated gain of 24.1 dB, a saturated output power (Psat) of 12.1 dBm, a maximum power-added efficiency (PAEmax) of 9.8 % and an output power at the 1 dB compression point (P1dB) of 8 dBm using a supply voltage of 0.81 V. The stacked PA achieves a gain of 18.9 dBm, Psat of 13.6 dBm, PAEmax of 14.6 % and P1dB of 10.4 dBm using a supply voltage of 2.25 V. Additionally simulations using AWR Microwave Office is performed to evaluate the system performance of the PAs when transmitting at a data rate of 100 Gbps. The PDCS PA and stacked PA achieved a maximum output power of 3.6 dbM and 6.5 dBm respectively at the error vector magnitude (EVM) limit of 3.5 % for 256 QAM signals. For 64 QAM signals they achieved a maximum output power of 6.5 and 8 dBm respectively at the EVM limit of 5.5 %.